• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    PURPOSE:To ensure a faithful correction of a time base error by detecting a velocity error with a horizontal synchronous signal and a burst signal, and, on the basis of the velocity error signal, by reading a composite information signal in which a time base error has been corrected.
    公开号:SU1718744A3
    申请号:SU773267800
    申请日:1977-04-09
    公开日:1992-03-07
    发明作者:Ниномия Такеси
    申请人:Сони Корпорейшн (Фирма)；
    IPC主号:
    专利说明:

    The sensor, the outputs of the speed error recording block are connected via AND elements to the corresponding control inputs of the recording keys, the second inputs of the AND elements are combined, and through the OR element are connected to the control inputs of the first and second switches and the output of the second standby multivibrator, whose input is connected via a key to the input of the trigger signal, the control input of the key is the input of the control logic signal, the third address input is the input of the digital adder, the output of which is connected to the second input of the second reklyuchatel, whose output is connected to the input velocity error recording unit, the second input of the OR gate is connected to the output of the second monostable multivibrator, and the output of the memory
    sweep errors are merged. read key outputs.
    2. A device according to claim 1, in which the impulse generator OPTIC contains, in series, a midpoint: sawtooth voltage generator, a phase modulator, a multivibrator, a band-pass filter and an amplifier, and a pulse shaper, the output of which is the output of a read pulse generator, the first and second inputs of which are, respectively, the second input of the phase modulator and the first input of the sawtooth generator, the second input of which is connected to the output of the inverter, the input of which is sync signal.
    The invention relates to television technology and can be used in video recording and standard conversion.
    The purpose of the invention is to improve the accuracy of the correction of temporal distortions.
    Figure 1 shows a structural electrical circuit of a time distortion correction device; Figures 2 and 3 are structural block diagrams, respectively, of a scan memory error block and a read pulse generator.
    The time distortion correction device comprises an information input unit 1, a memory unit 2, an information output unit 3, a memory control unit 4, a control unit 5, a sync selector 6, a flash signal extraction unit 7, a recording clock generator 8, a pulse driver-9 .sov, detector 10 signal loss unit
    11measuring the sweep error, block
    12 through sweep errors, a 13 read pulse generator, a synchronous generator 14, and a defect memory block 15.
    The information input unit 1 comprises a demodulator 16, a controlled amplifier 17, a sampling and storage element 18, an amplifier 19 and an analog-to-digital converter 20. The information output unit 3 contains a buffer memory element 21, a digital-to-analog converter 22 and a mixer 23.
    Block 12 (FIG. 2) of the sweep error memory comprises a digital adder 24, a speed error recording unit 25, a read error recording unit 26, write keys 27, read keys 28, amplifiers 29, capacitors 30, elements 31, and OR element 32 , the first 33 and second 34 standby multivibrators, the first 35 and second 36 switches, the key 37 and the buffer amplifier 38.
    The read pulse generator 13 (FIG. 3) comprises a sawtooth voltage generator 39, a phase modulator 40, a multivibrator 41, a band pass filter 42, an amplifier 43, a pulse shaper 44 and an inverter 45.
    The device works as follows.
    zom.
    The input video signal is fed to the demodulator 16 of block 1. The resulting NTSC video signal is fed through the controlled amplifier 17 to the element 18 and
    further through the amplifier 1-9 to analog-to-digital converter 20.. .
    The recovered NTSC video signals are fed to a sync selector 6, which selects the synchronization signals horizontally, as well as to block 7, which is controlled by the selected horizontal synchronization signals such
    to extract flash signals from NTSC video signals. The horizontal synchronized signals and the flash signals thus extracted are fed to generator 8, which generates high-frequency WRCK write pulses (approximately 10.74 µHz), i.e.
    a frequency that is three times the frequency f of the color subcarrier of the NTSC signals, and their frequency or speed / repetition and phase change according to changes in the frequency and phase of the signals
    horizontal synchronization, as well as flash signals separated from the input video signals and dependent on the time axis errors in the specified input signals.
    Separated horizontal synchronization signals arrive at shaper 9, which generates WST recording pulses at predetermined intervals, for example, at the beginning of each horizontal or linear interval of input video signals, if digital information corresponding to one horizontal or linear interval is to be recorded in memory block 2.
    WST recording start pulses. as well as WRCK write synchronization pulses are applied to the control unit 5, which controls the operation of the memory control unit 4, ensuring the selective execution of recording and reproducing operations.
    To determine the sync rate at which digitized information is read from memory block 2, there is a clock generator 14 that generates a fixed or standard frequency carrier signal, such as a standard frequency f with a color subcarrier of 3.58 MHz for NTSC color video signals, supplying the specified sigma 13 pulse readout generator;
    The RCK read clock pulses are also transmitted to the buffer memory element 21, which receives the digitized information sequentially read from Block 2, as well as the digital-to-analog converter 22, which is commissioned to invert the digital output signal into analog form. The analog output signal is then fed to a mixer 23, which also receives a standard frequency carrier signal from a sync generator 14 and is commissioned to sum up the flash signal and the analogue clock signal 22, which are pre-separated from the input video signals, to the output signal:
    To correct for varying temporal errors that may occur in the input video signals, the device additionally determines the speed error of the generator 8 during the recording period, and then sends the speed error signal to the memory block 12 using the measurement block 11. The memory unit 12, controlled by the control unit 5, memorizes the speed error detected during the recording period, and during the reading period, the corresponding speed error correction signal from the memory unit 12 is fed to the synchronous generator 14, where the generator output signal is modulated 13 (RCK pulses), corresponding to the full and switching or compensation of speed errors. Thus, the synchronizing PM read pulses RCK, having a standard frequency at the beginning and end of each reading period, can undergo
    5 changes in phase during the indicated reading period.
    The correction device is equipped with a signal loss detector 10, which forms a corresponding signal.
    0 interruptions supplied to the control unit 5, as well as to the defect memory block 15, in which information relating to defects in the input video signals is stored and then used to select sequentially reads from memory blocks 2 and 12, as well as for recording in the latest video information, free from loss, in such a way as to exclude the said disappearance from video signals with a corrected time axis.
    The speed error, measured in block 11, is fed to the input of the first switch 35 (FIG. 2), which supplies the speed error signal to the buffer amplifier 38. The first
    35, the switch is moved to the position corresponding to the closure of input A only during the rewriting in block 2 by the video information overwriting signal PRWRA identified by the final
    .0 FDRA Read Address. The key 3.7 closes as a result of the presence of a high level (1) of the logical output signal LG at the input of the second waiting multivibrator 34. The waiting multivibrator 34 forms
    5 is a relatively high level 1 output with a duration of approximately 20 µs. This output signal is fed to the first switch 35 to move it to the position corresponding to closing contact A, and the second switch 36, the movable contact of which in normal operation is in position B (Fig. 2), to which a signal from the digital adder 24 is applied. Moving contact
    5 of the second switch 36 is connected to block 25.
    During the write operation to memory block 2, identified by the WRA address, block 25 delivers the corresponding control signal to one of the AND 31 elements. A 40: µs pulse, fed through the second waiting multivibrator 34 and the OR 32 element to all the elements And 31, closes the corresponding entry key 27. After locking the selected of the keys 27, the speed error signal, measured in block 11, is fed through the buffer amplifier 38 and the key 27 to
    corresponding capacitor 30 and amplifier 29.
    Thus, during the execution of the recording operation of the digital video information in the memory block 2, a signal about the sweep speed error is recorded in the next recording interval in the corresponding capacitor 30.
    In order to read the speed error information during a normal read operation from memory block 2, a final read address is provided to block 26. Block 26 may generate control signals to selectively close normal open keys. 28, located between the outputs of the buffer amplifiers 29 and the output of the block 12.
    In the generator 13 read pulses, there is a pilot voltage generator 39, which receives a speed error signal from the output of block 12. Next, the read command RCD goes to inverter 45. The output of which is connected to generator 39 in such a way that the output signal of the latter remains zero during the time interval when the output signal of the inverter 45 is high (1), i.e. during the time intervals
    between successive RCD read commands. The SC subcarrier signal, for example, having a frequency of 3.58 MHz in the case of processing a color NTSC video signal, comes from a clock 14 to a phase modulator 40 designed to modulate in phase according to the output signal of the sawtooth 39.
    The phase-modulated subcarrier signal is applied to the multivibrator 41, which forms an appropriately phase-modulated rectangular signal as well as its harmonics. The output of the multivibrator is fed to a band-pass filter 42, which is tuned to the third harmonic of the SC subcarrier signal so that the phase-modulated output of the band-pass filter 42 has a frequency of, for example, 10.74 MHz. The output of the bandpass filter 4.2 is fed through an amplifier 43 to a pulse shaper 44 in order to obtain the required read clock RQK modulated by the magnitude of the speed error and determine the synchronization rate with which the digitized video data is read from memory block 2.
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    权利要求:
    Claims (2)
    [1]
    1. DEVICE FOR CORRECTION OF TEMPORARY DISTORTIONS, containing subsequently connected information input unit, memory unit and information output unit, control unit and memory control unit connected in series, the output of which is connected to the control input of the memory unit, a read pulse generator, the first input of which is connected to the second the output of the control unit, and the output is connected to the first control input of the memory control unit, between the second output of the information input unit and the first input of the control unit in series the sync selector and the recording clock generator are switched on, the second input of which is connected to the output of the flash signal extraction unit, the first input of which is connected to the sync selector input, and the second to the sync selector output, the first output of the recording clock is connected to the second control input of the memory control unit, It is interesting that in order to increase the accuracy of the correction of temporary distortions, a block has been introduced. sweep error memory and block Sweep error measurement, with the second, third and fourth outputs of the general ; 2;
    a torus of write clock pulses are connected respectively to the first and second inputs of the sweep error measurement unit and to the first input of the sweep error memory block, the second input of which is connected to the output of the sweep error measurement unit, the group of control inputs of the sweep error memory unit is connected to the corresponding group of outputs of the control unit, and the output of the scan error memory block is connected to the second input of the read pulse generator, while the scan error memory block contains digital a new adder, a speed error recording unit, a reading error recording unit, a group of writing keys, a group of reading keys, a group of AND elements, a group of amplifiers, a group of capacitors, a first and second standby multivibrators, an ILI element, the first and second switches and switch ^, the group control inputs of the scan error memory block consists of the first, second and third address inputs, the start signal input and the logical control signal input, the first address input is the input of the read error recording unit, the outputs are orogo connected to respective control inputs of the read key, whose outputs are combined and connected to the first input of the first switch, and an output; through the corresponding amplifiers are connected to the outputs of the corresponding keys; recordings, the corresponding capacitors are connected in parallel to the inputs of the amplifiers, and the inputs of the recording keys are combined and connected to the second input of the first switch, the third input of which is the second input of the scan error memory block, the second address input of which is the first input of the second switch
    SU <.,> 1718744 AZ
    No. 718744 of the sensor, the outputs of the speed error recording unit through the AND elements are connected to the corresponding control inputs of the recording keys, the second inputs of the AND elements are combined and through the OR element are connected to the control inputs of the first and second switches and to the output of the second multivibrator, the input of which is connected through the key to the input trigger signal, the control input of the key is the input of the logical control signal, the third address input is the input of the digital adder, the output of which is connected to the second input of the second a switch whose output is connected to the input of the speed error recording unit, the second input of the OR element is connected to the output of the second standby multivibrator, and the output of the readout error memory are the combined! ^ read key outputs. i
    [2]
    2. Device pop. 1, characterized in that the read pulse generator contains serially connected sawtooth voltage generator, phase modulator, multivibrator, band-pass filter and amplifier, and a pulse shaper, the output of which is the output of the read pulse generator, the first and second inputs which are respectively the second input of the phase modulator and the first input of the sawtooth voltage generator, the second input of which is connected to the output of the inverter, the input of which is the input of the signal ronizatsii.
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    同族专利:
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    SE7607898L|1977-01-12|
    NL7607708A|1977-01-13|
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    IT1192138B|1988-03-31|
    SE438936B|1985-05-13|
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    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    JPS5320169B2|1972-04-24|1978-06-24|
    JPS5011314A|1973-05-30|1975-02-05|
    US3860952B2|1973-07-23|1996-05-07|Harris Corp|Video time base corrector|
    US4063284A|1974-12-25|1977-12-13|Sony Corporation|Time base corrector|US4074307A|1975-08-14|1978-02-14|Rca Corporation|Signal processor using charge-coupled devices|
    JPS5838011B2|1976-07-05|1983-08-19|Sony Corp|
    JPS6150432B2|1977-05-31|1986-11-04|Sony Corp|
    JPS6246110B2|1978-04-28|1987-09-30|Sony Corp|
    JPS60142859U|1984-02-29|1985-09-21|
    JPH0438197B2|1984-11-26|1992-06-23|Sharp Kk|
    JPH0712229B2|1984-12-25|1995-02-08|ソニー株式会社|Time axis correction device|
    DE3533702C2|1985-09-21|1992-07-02|Bts Broadcast Television Systems Gmbh, 6100 Darmstadt, De|
    JP2501195B2|1986-04-30|1996-05-29|シャープ株式会社|Color image processing device|
    JPH0620293B2|1986-09-17|1994-03-16|パイオニア株式会社|Time axis error correction device|
    JP4875035B2|2008-09-10|2012-02-15|株式会社東芝|Video recording / playback device|
    法律状态:
    优先权:
    申请号 | 申请日 | 专利标题
    JP8563175A|JPS555956B2|1975-07-11|1975-07-11|
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